www.latticesemi.com 1 an6059_01.1 isppac-powr1208p1 evaluation board pac-powr1208p1-ev march 2007 application note an6059 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. introduction the lattice semiconductor isppac -powr1208p1 in-system-programmable analog circuit allows designers to implement both the analog and digital functions of a power supply monitoring and sequencing subsystem within a single integrated circuit. by integrating analog functions such as comparators and programmable slew rate fet drivers with the digital functionality of a programmable logic device (pld), the isppac-powr1208p1 provides the power-supply designer with a rich set of features in a single device. isp (in-system-programmability) provides the designer with an unprecedented level of ?xibility, allowing him to con?ure analog parameters such as threshold voltages as well as de?ing state machines and combinatorial logic functions. all con?uration data is stored internally in e 2 cmos nonvolatile memory. programming a con?uration is accomplished through an industry-standard jtag ieee 1149.1 interface. pac-powr1208p1-ev evaluation board the pac-powr1208p1-ev evaluation board (figure 1) allows the designer to quickly con?ure and evaluate the isppac-powr1208p1 on a fully assembled printed-circuit board. the double-sided board supports a 44-pin tqfp package, a header for user i/o, a jtag programming cable connector, and an uncommitted pad array for user pro- totyping. jtag programming signals can be generated by using an ispdownload programming cable con- nected between the evaluation board and a pc s parallel (printer) port. both analog and digital features of the isppac-powr1208p1 can be easily con?ured using pac-designer software. figure 1. pac-powr1208p1-ev evaluation board
isppac-powr1208p1 evaluation board lattice semiconductor pac-powr1208p1-ev 2 a complete schematic for the evaluation board is shown in figure 2. figure 2. schematic programming interface lattice semiconductor s ispdownload cable can be used to program the isppac-powr1208p1 on the evalua- tion board. this cable plugs into a pc-compatible s parallel port connector, and includes active buffer circuitry inside its db-25 connector housing. the other end of the ispdownload cable terminates in an 8-pin 0.100 pitch header connector which plugs directly into a mating connector provided on the pac-powr1208p1-ev evaluation board. prototype area a 19x18 grid (0.100 pitch) of uncommitted, plated through holes with annular-ring pads is provided as a user pro- totyping area. adjacent to this uncommitted array are two 19-hole rows providing easy connections to both power and ground. this prototyping area allows the user to build small circuits directly on the evaluation board. in the case of larger circuits, the evaluation board can be readily connected into off-board circuitry through p5, into which can be mounted a 20 x 2 header. power supply considerations the isppac-powr1208p1 operates with power supplies ranging from 2.7v to 5.5v, and allows for separate core (vdd) and i/o (vddinp) voltages. voltages ranging from 0 to 5.94v may be monitored at any of the 12 vmonx vmon1 vmon2 vmon3 vmon4 vmon5 vmon6 vmon7 vmon8 vmon9 vmon10 vmon11 vmon12 in1 in2 in3 in4 vmon1 vmon2 vmon3 vmon4 vmon5 vmon6 vmon7 vmon8 vmon9 vmon10 vmon11 vmon12 in1 in2 in3 in4 32 33 34 35 36 37 38 40 41 42 43 44 6 7 8 9 por por 25 comp1 comp1 23 comp2 comp2 22 comp3 comp3 21 comp4 comp4 20 comp5 comp5 19 comp6 comp6 18 comp7 comp7 17 comp8 comp8 16 vdd reset reset 10 vdd vddinp j7.5 c1 0.1u c3 0.1u vdd vddinp 5 11 vdd vddinp j9 vdd vddinp c5 4.7u vdd vddinp vddinp cref gnd 39 27 c2 1u 30 24 31 28 tdi tck tms tdo s ch tdi tdo tms tck hvout1 4 hvout2 3 hvout3 2 hvout4 1 hvout1 hvout2 hvout3 hvout4 out5 out6 out7 out8 out5 out6 out7 out8 15 14 13 12 vdd vdd gnd tdi tdo tms tck vdd gnd vdd p5 p2 p1 p5 isppac-powr1208p1 r1d 470 r1e 470 r1f 470 r1g 470 r10 2k r9 2k r8 2k r7 2k j7.1 j7.2 j7.3 j7.4 j8 r2 10k c4 0.1u sw1 reset r1b 470 led power r3 2k r4 2k r5 2k r6 2k led out5 led out6 led out7 led out8 tdo led r1c 470 clk clk 26
isppac-powr1208p1 evaluation board lattice semiconductor pac-powr1208p1-ev 3 pins independent of the values of vdd and vddinp. for device programming, however, vdd must be set between 3.0 and 5.5v. on the evaluation board, vdd and vddinp are normally connected together with a user-removable jumper (j7.5). this jumper can be removed to allow for independent vdd and vddinp supplies. input/output connections connectors are provided for key functions and test points on this evaluation board, as shown in figure 3. power is supplied through two color coded (red = +, black = -) banana jacks in the upper right corner of the board. the jtag programming cable is connected to a keyed header (p1) in the lower right corner of the board. a pcb land pattern is provided for the addition of an additional jtag interface header (p2) to allow for connecting multiple pac-powr1208p1-ev evaluation boards into a multi-device programming chain. access to the isppac-powr1208p1 s i/o pins is available at p5, which is a 2x20 row of pads to which one may attach test probes or a ribbon-cable connector. at this point all of the device s i/o pins (except those required for the jtag programming interface) are accessible. figure 3. i/o and jumpers jumper options several jumpers are provided on the evaluation board to make it simple to implement common circuit con?ura- tions. these jumpers are: j7 - positions 1-4 connect pull-up resistors to the high voltage outputs hvout1-4, and allow the user to enable the pull-ups on an output-by-output basis. the pull-up voltage is selected by j8. position 5 (the right- most position) is used to connect vddinp to vdd, and should normally be left in place. this jumpers needs to be removed when using separate vdd and vddinp supplies. j8 - selects a pull-up voltage to which the high-voltage outputs (hvout1-4) may be pulled up to, either vdd or vddinp. isppac- powr1208p1 1 p1 jtag interface vdd gnd p5 j9 j8 j7 1234 vdd vddinp vdd vddinp vdd vddinp out[5-8] hvout[1-4] hvout pull-up out8 out7 out6 out5 power tdo reset vmon1 vmon2 vdd vmon11 vmon9 vmon7 vmon12 vmon10 vmon8 vmon6 vmon4 vmon5 vmon3 in2 in4 vddinp gnd out5 hvout3 hvout1 in1 in3 reset gnd gnd out6 out8 comp7 comp5 comp3 comp1 clk out7 comp8 comp6 comp4 comp2 por hvout4 hvout2
isppac-powr1208p1 evaluation board lattice semiconductor pac-powr1208p1-ev 4 j9 - selects whether open-drain digital outputs out5-out8 are pulled up to vdd (upper position), vddinp (lower position), or not pulled up at all. these outputs are pulled up through 2k resistors. controls and indicators a reset switch is provided on the evaluation board which pulls the reset input pin low when it is depressed, re-ini- tializing the isppac-powr1208p1. leds are also provided as an aid to debugging. one led shows whether the board has power applied, while another is connected to the jtag tdo line, and will ?sh when a download is being performed. additionally, four leds are attached to the isppac-powr1208p1 s out5-out8 lines. by adding appropriate code to the sequencer program, these leds can be made to indicate the internal status of the isppac-powr1208p1, and can be a useful debug aid. pcb artwork figure 4. silk screen
isppac-powr1208p1 evaluation board lattice semiconductor pac-powr1208p1-ev 5 figure 5. top-side foil figure 6. bottom-side foil
isppac-powr1208p1 evaluation board lattice semiconductor pac-powr1208p1-ev 6 component list ordering information technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: isppacs@latticesemi.com internet: www .latticesemi.com revision history quantity ref. designators description 2 c1, c3 0.1? capacitor 1 c2 1? capacitor 1 c4 0.1? capacitor 1 c5 4.7? capacitor 1 j7 2 x 5 header strip, dual row, 0.1 spacing 2 j8,j9 1 x 3 header strip, single row, 0.1 spacing 5 led_a, led_b, led_c, led_d, power_led t-1-3/4 red led 1 p1 1x8 header strip, single row, 0.1 spacing 1 p3 red banana jack 1 p4 black banana jack 1 r1 470 ohm sip-8 resnet, 7-resistor sip, bussed type 1 r2 10k resistor 8 r3, r4, r5, r6, r7, r8, r9, r10 2k 5% resistor 1 sw3 pushbutton switch 1 tdo_led t1-3/4 green led 1 u1 isppac-powr1208p1 description ordering part number china rohs environment-friendly use period (efup) isppacpowr1208 precision evaluation board pacpowr1208p1-ev isppac power manager 1208 precision design system pac-syspowr1208p1 date version change summary february 2005 01.0 previous lattice releases. march 2007 01.1 added ordering information section. 10
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